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DDR3-1333 SDRAM 8GB ECC REG CL9 DIMM DR Print
March 2011
This page describes ValueRAM's 1024M x 72-bit 8GB (8192MB) DDR3-1333MHz CL9 SDRAM (Synchronous
DRAM) registered w/parity, dual-rank memory module, based on thirty-six 512M x 4-bit DDR3-1333MHz FBGA
components. The SPD is programmed to JEDEC standard latency 1333MHz timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact fingers and requires +1.5V. The electrical and mechanical specifications are as follows:

Description: 8GB 1333MHz DDR3 ECC Reg CL9 DIMM DR x4 w/TS
Detailed Specifications: Standard 1024M X 72 ECC 1333MHz 240-pin Registered DIMM (DDR3, 1.5V, CL9, FBGA, Gold)

Features:
  • JEDEC standard 1.5V ± 0.075V Power Supply
  • VDDQ = 1.5V ± 0.075V
  • 667MHz fCK for 1333Mb/sec/pin
  • 8 independent internal bank
  • Programmable CAS Latency: 6,7,8,9,10
  • Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
  • Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
  • 8-bit pre-fetch
  • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4
  • which does not allow seamless read or write [either on the fly using A12 or MRS]
  • Bi-directional Differential Data Strobe
  • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
  • On Die Termination using ODT pin
  • On-DIMM thermal sensor (Grade B)
  • Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C
  • Asynchronous Reset
  • PCB : Height 1.180” (30.00mm), double sided component
Performance:

CL(IDD)
 9 cycles
Row Cycle Time (tRCmin) 49.5ns (min.)
Refresh to Active/Refresh Command Time (tRFCmin) 160ns
Row Active Time (tRASmin) 36ns (min.)
Power 4.365 W (operating)
UL Rating
 94 V - 0
Operating Temperature
 0 C to 85 C
Storage Temperature
 -55 C to +100 C


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1E33G8R
 
DDR3-1333 SDRAM 4GB ECC REG CL9 DIMM DR Print
March 2011
This page describes ValueRAM's 512M x 72-bit 4GB (4096MB) DDR3-1333 CL9 SDRAM (Synchronous DRAM)
registered w/parity, dual-rank memory module, based on thirty-six 256M x 4-bit DDR3-1333 FBGA components. The SPD is programmed to JEDEC standard latency 1333Mhz timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact fingers and requires +1.5V. The electrical and mechanical specifications are as follows:

Description: 4GB 1333MHz DDR3 ECC Reg CL9 DIMM DR x4 w/TS
Detailed Specifications: Standard 512M X 72 ECC 1333MHz 240-pin Registered DIMM (DDR3, 1.5V, CL9, FBGA, Gold)

Features:
  • JEDEC standard 1.5V ± 0.075V Power Supply
  • VDDQ = 1.5V ± 0.075V
  • 667MHz fCK for 1333Mb/sec/pin
  • 8 independent internal bank
  • Programmable CAS Latency: 6,7,8,9,10
  • Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
  • Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
  • 8-bit pre-fetch
  • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4
  • which does not allow seamless read or write [either on the fly using A12 or MRS]
  • Bi-directional Differential Data Strobe
  • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
  • On Die Termination using ODT pin
  • On-DIMM thermal sensor (Grade B)
  • Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C
  • Asynchronous Reset
  • PCB : Height 18.75mm, double sided component
Performance:

CL(IDD)
 9 cycles
Row Cycle Time (tRCmin) 49.5ns (min.)
Refresh to Active/Refresh Command Time (tRFCmin) 110ns
Row Active Time (tRASmin) 36ns (min.)
Power 3.960 W (operating)
UL Rating
 94 V - 0
Operating Temperature
 0 C to 85 C
Storage Temperature
 -55 C to +100 C


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1E33G4R
 
DDR3-1600 SDRAM 4GB ECC CL11 with Thermal Sensor Print
March 2011
This high-density memory module consists of 18 pieces 256M x 8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM. The module is a 240-pins dual in-line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. The following provides general specifications of this module.

Description: DDR3-1600 SDRAM 4GB ECC CL11 with Thermal Sensor

Features:
  • Double-date-rate architecture: 2 data transfers per clock cycle
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted /received with data for capturing data at the receiver
  • DQS is edge-aligned with data for READs; center aligned with data for WRITEs
  • Differential clock inputs (CK and /CK)
  • Posted CAS
  • DLL aligns DQ and DQS transitions with CK transitions
  • Data mask (DM) for writing data
  • Posted /CAS by programmable additive latency for enhanced command and data bus efficiency
  • On-Die-Termination (ODT) for improved signal quality: Synchronous ODT/Dynamic ODT/Asynchronous ODT
  • Multi-Purpose Register (MPR) for temperature read out
  • ZQ calibration for DQ drive and ODT
  • SRT range: normal/extended, auto/manual self-refresh
  • Programmable output driver impedance control
  • Commands entered at each positive clock input, while data and data mask are referenced to both edges of DQS
Performance

CL(IDD)
 11 cycles
Row Cycle Time (tRCmin)  48.75ns (min.)
Refresh to Active/Refresh Command Time (tRFCmin)  160ns
Row Active Time (tRASmin)  35ns (min.)
Power supply VDD:  1.5V ± 0.075V
UL Rating
 94 V - 0
Operating Temperature
 0 C to 85 C
Storage Temperature
 -55 to +100


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1E33G4
 
DDR3-1333 SDRAM 2GB ECC REG CL9 DIMM DR Print
March 2011
This page describes ValueRAM's 256M x 72-bit 2GB (2048MB) DDR3-1333MHz CL9 SDRAM (Synchronous
DRAM) registered w/parity, dual-rank memory module, based on eighteen 128M x 8-bit DDR3-1333MHz FBGA
components. The SPD is programmed to JEDEC standard latency 1333MHz timing of 9-9-9 at 1.5V. This 240-pin DIMM
uses gold contact fingers and requires +1.5V. The electrical and mechanical specifications are as follows:

Description: 2GB 1333MHz DDR3 ECC Reg CL9 DIMM DR x8 w/TS
Detailed Specifications: Standard 256M X 72 ECC 1333MHz 240-pin Registered DIMM (DDR3, 1.5V, CL9, FBGA, Gold)

Features:
  • JEDEC standard 1.5V ± 0.075V Power Supply
  • VDDQ = 1.5V ± 0.075V
  • 667MHz fCK for 1333Mb/sec/pin
  • 8 independent internal bank
  • Programmable CAS Latency: 6,7,8,9,10
  • Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
  • Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
  • 8-bit pre-fetch
  • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4
  • which does not allow seamless read or write [either on the fly using A12 or MRS]
  • Bi-directional Differential Data Strobe
  • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
  • On Die Termination using ODT pin
  • On-DIMM thermal sensor (Grade B)
  • Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C
  • Asynchronous Reset
  • PCB : Height 1.180” (30.00mm), double sided component

Performance:

CL(IDD)
 9 cycles
Row Cycle Time (tRCmin)  49.5ns (min.)
Refresh to Active/Refresh Command Time (tRFCmin)  110ns
Row Active Time (tRASmin)  36ns (min.)
Power  3.480 W (operating)
UL Rating
 94 V - 0
Operating Temperature
 0 C to 85 C
Storage Temperature
 -55 C to +100 C


Click here to return
1E33G2R
 
DDR3-1600 SDRAM 2GB ECC CL11 with Thermal Sensor Print
March 2011
This high-density memory module consists of 9 pieces 256M x 8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM. The module is a 240-pins dual in-line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. The following provides general specifications of this module:

Description: DDR3-1600 SDRAM 2GB ECC CL11 with Thermal Sensor


Features
  • Double-date-rate architecture: 2 data transfers per clock cycle
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted /received with data for capturing data at the receiver
  • DQS is edge-aligned with data for READs; center aligned with data for WRITEs
  • Differential clock inputs (CK and /CK)
  • Posted CAS
  • DLL aligns DQ and DQS transitions with CK transitions
  • Data mask (DM) for writing data
  • Posted /CAS by programmable additive latency for enhanced command and data bus efficiency
  • On-Die-Termination (ODT) for improved signal quality: Synchronous ODT/Dynamic ODT/Asynchronous ODT
  • Multi-Purpose Register (MPR) for temperature read out
  • ZQ calibration for DQ drive and ODT
  • Programmable Partial Array Self-Refresh (PASR)
  • /Reset pin for power-up sequence and reset function
  • SRT range: normal/extended, auto/manual self-refresh
  • Programmable output driver impedance control
  • Commands entered at each positive clock input, while data and data mask are referenced to both edges of DQS
Performance

CL(IDD)
 11 cycles
Row Cycle Time (tRCmin)  48.75ns (min.)
Row Active Time (tRASmin)  35ns (min.)
Power  1.5V  (operating)
Operating Temperature
 0 C to 85 C
Storage Temperature
 -55 C to +100 C


Click here to return
1E33G2
 
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