This article attempts to provide the basis for assessing the fitness of computer platforms for desktops and servers.  The discussions refer to Von Neumann system architecture as all other architectures do not have a similar level of market dominance.

Von Neumann Stored Program Architecture

o The architecture was first known in 1945 and has slightly evolved to mean a stored program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. It keeps its programmed instructions and data in RAM (random access memory).  Modern processors include separate instruction cache and data cache on the CPU die, but they are still considered Von Neumann in this article.  The original Harvard Architecture was meant to have separate bus and spaces for instructions and data, and the modified version applies separation at the cache level and not main memory.  As such, there is a universal concern on the single bus arrangement creating a performance bottleneck. 

Connectivity of Modern x86 Systems

o Modern desktop processors such as Intel Core and AMD APU have incorporated the GPU, memory controller, display controller, and PCIe controller inside the CPU die.  They are close in design to System-on-Chip (SOC) such as Intel Atom Centerton which includes the above lot and other I/O controllers on die.  Intel Core and AMD APU employ a south bridge to handle low speed I/O device control.  Note: The GPU mentioned above is normally for display purposes and not in the class that Nvidia touted for high performance general purpose computing.

o In terms of connectivity, the CPU interfaces with memory and display devices through dedicated controllers, and with other devices through the PCIe controller.  Display devices go through the PCIe controller as well for some modern CPU designs.  As such, the memory controller and PCIe controller have crucial roles in deciding the performance of a computer.

o Compucon system platform design philosophy carries the caution that a system is as strong as its weakest link.  In reality, not all applications have the same appetite for different resources of a computer system and this “as strong as weak link” concept shall be modified to adapt.

Bottleneck of Computing Sub-system

o Is the CPU continually forced to wait for needed data to be transferred to or from memory?  One answer comes from the Arithmetic Intensity (see separate article) required by the application relative to the CPU design.  AI is the ratio of CPU processing rate to memory data transfer rate. 

o The current memory type is DDR3.  It is known to have a high latency (lead time before data transfer takes place) and current efforts for DDR4 development are to reduce the latency.  Intel E5 Xeon and Core 2011p i7 processors have 4 memory controllers- Intel website has quoted a memory transfer rate of 51GB/s for DDR3.  We guess the same processors may hit 100GB/s if DDR4 is used.

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This article attempts to provide the basis for assessing the fitness of computer platforms for desktops and servers.  The discussions refer to Von Neumann system architecture as all other architectures do not have a similar level of market dominance.

Von Neumann Stored Program Architecture

o The architecture was first known in 1945 and has slightly evolved to mean a stored program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. It keeps its programmed instructions and data in RAM (random access memory).  Modern processors include separate instruction cache and data cache on the CPU die, but they are still considered Von Neumann in this article.  The original Harvard Architecture was meant to have separate bus and spaces for instructions and data, and the modified version applies separation at the cache level and not main memory.  As such, there is a universal concern on the single bus arrangement creating a performance bottleneck. 

Connectivity of Modern x86 Systems

o Modern desktop processors such as Intel Core and AMD APU have incorporated the GPU, memory controller, display controller, and PCIe controller inside the CPU die.  They are close in design to System-on-Chip (SOC) such as Intel Atom Centerton which includes the above lot and other I/O controllers on die.  Intel Core and AMD APU employ a south bridge to handle low speed I/O device control.  Note: The GPU mentioned above is normally for display purposes and not in the class that Nvidia touted for high performance general purpose computing.

o In terms of connectivity, the CPU interfaces with memory and display devices through dedicated controllers, and with other devices through the PCIe controller.  Display devices go through the PCIe controller as well for some modern CPU designs.  As such, the memory controller and PCIe controller have crucial roles in deciding the performance of a computer.

o Compucon system platform design philosophy carries the caution that a system is as strong as its weakest link.  In reality, not all applications have the same appetite for different resources of a computer system and this “as strong as weak link” concept shall be modified to adapt.

Bottleneck of Computing Sub-system

o Is the CPU continually forced to wait for needed data to be transferred to or from memory?  One answer comes from the Arithmetic Intensity (see separate article) required by the application relative to the CPU design.  AI is the ratio of CPU processing rate to memory data transfer rate. 

o The current memory type is DDR3.  It is known to have a high latency (lead time before data transfer takes place) and current efforts for DDR4 development are to reduce the latency.  Intel E5 Xeon and Core 2011p i7 processors have 4 memory controllers- Intel website has quoted a memory transfer rate of 51GB/s for DDR3.  We guess the same processors may hit 100GB/s if DDR4 is used.

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This note explains the use of video analytics to detect a few scenarios of human behaviour that may need follow-up actions by another party. The scenarios covered here (as listed below) were classified as iQ-115 to reflect the intelligence level of the application. 

-Slip and fall
-Loitering
-Run or speed

Pre-requisite

The minimum hardware is a video surveillance camera connected to a PC based system that runs a Video Analytics software application. The VA application has to be set up in advance correctly. These are the essential and minimum set up:

Slip and Fall

This application detects human slip and fall in public or private places such as retirement homes or hospitals.  When slip or fall is detected, the system will send an alarm or alert message to another party for follow up action.  The message will include a snapshot of the slip or fall so that the other party can decide what to do next.  To reduce alarming nuisance, the application will ignore slip or fall that take place very slowly such as people bending to tie shoe lace or stretching when tired.  This requires a set up in advance of a short time period (several seconds) for qualifying motions.

Loitering

Loitering can be harmful to public or private safety or security because criminals loiter a while before launching an attack.  Loitering will certainly be picked up by a surveillance camera on motion detection basis among all other situations such as environmental illumination intensity change without discrimination.  Detection of loitering does require special treatment in terms of a longer time period (such as 15 seconds) for qualifying motions.  This may not work well in a crowded scene as obstructions by a different object will reset the clock to count again.

Run and Speed

Someone is rushing (moving faster than normal).  It can be a robbery.  It can be the start of a fight.  It can be many other things too.  Irrespectively we can look at what has happened and decide if to respond or not.  To detect running, the area of monitoring must be several times of the distance of a long step so that the application is able to compute the speed of movement.   

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